Product description
The MCP33111-10 is a single-ended 12-bit, single-channel 1 Msps ADC featuring low power consumption and high performance, using a successive approximation register (SAR) architecture. The device operates with a 2.5V to 5.1V external reference (VREF), which supports a wide range of input full-scale range from 0V to VREF. The reference voltage setting is independent of the analog supply voltage
(AVDD) and is higher than AVDD. The conversion output is available through an easy-to-use simple SPI compatible 3-wire interface.
The device requires a 1.8V analog supply voltage (AVDD) and a 1.7V to 5.5V digital I/O interface supply voltage (DVIO). The wide digital I/O interface supply (DVIO) range (1.7V - 5.5V) allows the device to interface with most host devices (Master) available without using external voltage level shifters.
When the device is first powered-up, it performs a self-calibration to minimize offset, gain and linearity errors. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage was not fully settled during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration to restore optimum performance.
The ADC system clock is generated by an internal on-chip clock, therefore the conversion is performed independent of the SPI serial clock (SCLK). This device can be used for various high-speed and high-accuracy analog-to-digital data conversion applications, where design simplicity, low power, and no output latency are needed.
(AVDD) and is higher than AVDD. The conversion output is available through an easy-to-use simple SPI compatible 3-wire interface.
The device requires a 1.8V analog supply voltage (AVDD) and a 1.7V to 5.5V digital I/O interface supply voltage (DVIO). The wide digital I/O interface supply (DVIO) range (1.7V - 5.5V) allows the device to interface with most host devices (Master) available without using external voltage level shifters.
When the device is first powered-up, it performs a self-calibration to minimize offset, gain and linearity errors. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage was not fully settled during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration to restore optimum performance.
The ADC system clock is generated by an internal on-chip clock, therefore the conversion is performed independent of the SPI serial clock (SCLK). This device can be used for various high-speed and high-accuracy analog-to-digital data conversion applications, where design simplicity, low power, and no output latency are needed.