Features
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
135 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-Chip 2-cycle Multiplier
Non-volatile Program and Data Memories
64/128K Bytes of In-System Self-Programmable Flash
Endurance: 100,000 Write/Erase Cycles
Optional Boot Code Section with Independent Lock Bits
USB Bootloader programmed by default in the Factory
In-System Programming by On-chip Boot Program hardware activated after
reset
True Read-While-Write Operation
All supplied parts are preprogramed with a default USB bootloader
2K/4K (64K/128K Flash version) Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
4K/8K (64K/128K Flash version) Bytes Internal SRAM
Up to 64K Bytes Optional External Memory Space
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
USB 2.0 Full-speed/Low-speed Device and On-The-Go Module
Complies fully with:
Universal Serial Bus Specification REV 2.0
On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s
USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
Endpoint 0 for Control Transfers : up to 64-bytes
6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
Configurable Endpoints size up to 256 bytes in double bank mode
Fully independant 832 bytes USB DPRAM for endpoint memory allocation
Suspend/Resume Interrupts
Power-on Reset and USB Bus Reset
48 MHz PLL for Full-speed Bus Operation
USB Bus Disconnection on Microcontroller Request
USB OTG Reduced Host :
Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
for OTG dual-role devices
Provide Status and control signals for software implementation of HNP and SRP
Provides programmable times required for HNP and SRP
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
Real Time Counter with Separate Oscillator
Four 8-bit PWM Channels
Six PWM Channels with Programmable Resolution from 2 to 16 Bits
Output Compare Modulator
8-channels, 10-bit ADC
Programmable Serial USART
Master/Slave SPI Serial Interface
Byte Oriented 2-wire Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
48 Programmable I/O Lines
64-lead TQFP and 64-lead QFN
Operating Voltages
2.7 - 5.5V
Operating temperature
Industrial (-40°C to +85°C)
Maximum Frequency
8 MHz at 2.7V - Industrial range
16 MHz at 4.5V - Industrial range
See datasheet for full technical details.
